View CY8C22345-24SXI_4667577.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY8C21345, CY8C22345, CY8C22545
PSoC(R) Programmable System-on-ChipTM
Features

Powerful Harvard Architecture Processor: M8C Processor Speeds up to 24 MHz 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed 3.0V to 5.25V Operating Voltage Industrial Temperature Range: -40C to +85C Advanced Peripherals (PSoC Blocks) Six Analog Type "E" PSoC Blocks provide: * Single or Dual 8-Bit ADC * Comparators (up to Four) Up to Eight Digital PSoC Blocks provide: * 8 to 32-Bit Timers, Counters, and PWMs * One Shot, Multi Shot Mode Support in Timers and PWMs * PWM with Deadband Support in One Digital Block * Shift Register, CRC, and PRS Modules * Full Duplex UART * Multiple SPITM Masters or Slaves, Variable Data Length Support: 8, 9, ...,16-bit * Can be Connected to all GPIO Pins Complex Peripherals by Combining Blocks Shift Function Support for FSK Detection Powerful Synchronize Feature Support. Analog Module Operations can be Synchronized by Digital Blocks or External Signals. High Speed 10-Bit SAR ADC with Sample and Hold Optimized for Embedded Control Precision, Programmable Clocking: Internal 5% 24/48 MHz Oscillator across the Industrial Temperature Range High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL Optional External Oscillator, up to 24 MHz Internal/External Oscillator for Watchdog and Sleep Flexible On-Chip Memory: Up to 16K Bytes Flash Program Storage 50,000 Erase/Write Cycles Up to 1K Byte SRAM Data Storage In-System Serial Programming (ISSPTM) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Optimized CapSense Resource: Two IDAC Support up to 640 A Source Current to Replace External Resistor Two Dedicated Clock Resources for CapSense: * CSD_CLK: 1/2/4/8/16/32/128/256 Derive from SYSCLK * CNT_CLK: 1/2/4/8 Derive from CSD_CLK Dedicated 16-Bit Timers/Counters for CapSense Scanning Support Dual CSD Channels Simultaneous Scanning
Programmable Pin Configurations: 25 mA Sink on all GPIO Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 38 Analog Inputs on GPIO Configurable Interrupt on all GPIO Additional System Resources: 2 I CTM Slave, Master, and MultiMaster to 400 kHz, Supports Hardware Addressing Feature Watchdog and Sleep Timers User Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Supports RTC Block into Digital Peripheral Logic
Top Level Block Diagram
Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers
PSoC Core
Global Digital Interconnect SRAM 1K Interrupt Controller SROM
Global Analog Interconnect Flash 16K Sleep and Watchdog

CPU Core (M8C)
Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital Block Array
DBC DBC DCC DCC
ANALOG SYSTEM
Analog Input Muxing(L,R) Analog Ref
=
ROW 1
DBC DBC DCC DCC
Analog Block Array
CTE SCE CTE SCE CTE CTE
ROW 2
System Bus
CapSense Digital Resource
10-bit SAR ADC
Digital Clocks
MACs
I2C
POR and LVD System Resets
Internal Voltage Ref.
SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 001-43084 Rev. *H
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 16, 2009
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
PSoC(R) Functional Overview
The PSoC(R) family consists of many On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages. The PSoC architecture, shown in Figure 1, consists of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows the combining of all the device resources into a complete custom system. The PSoC family can have up to five IO ports connecting to the global digital and analog interconnects, providing access to eight digital blocks and six analog blocks.
Digital System
The Digital System is composed of eight digital PSoC blocks. Each block is an 8-bit resource that may be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Figure 1. Digital System Block Diagram
Port 3 Port 4 Port 2 Port 1 Port 0
Digital Clocks From Core
To System Bus
To Analog System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input Configuration
Row 0
DBC00 DBC01 DCC02
4 DCC03 4
Row Output Configuration 8
PSoC Core
The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 21 vectors, to simplify the programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 16 KB of Flash for program storage, 1K bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator). The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is required, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC), and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin can also generate a system interrupt on high level, low level, and change from last read.
8 8 Row Input Configuration 8
Row 1
DBC00 DBC01 DCC02 DCC03
Row Output Configuration
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
Digital peripheral configurations are:

PWMs (8 to 32-Bit) PWMs with Dead band (8 to 32-Bit) Counters (8 to 32-Bit) Timers (8 to 32-Bit) UART 8 Bit with Selectable Parity (Up to Two) SPI Master and Slave (Up to Two) Shift Register (1 to 32-Bit) I2C Slave and Master (One Available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32-Bit) IrDA (Up to Two) Pseudo Random Sequence Generators (8 to 32-Bit)
The digital blocks may be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This provides a choice of system resources for your application. Family resources are shown in Table 1 on page 3.
Document Number: 001-43084 Rev. *H
Page 2 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Analog System
The Analog System consists of a 10-bit SAR ADC and six configurable blocks. The programmable 10-bit SAR ADC is an optimized ADC that could be run up to 200 ksps with 1.5 LSB DNL and 2.5 LSB INL (true for VDD 3.0V and Vref 3.0V). External filters are required on ADC input channels for antialiasing. This ensures that any out-of-band content is not folded into the input signal band. Reconfigurable analog resources allow creating complex analog signal flows. Analog peripherals are very flexible and may be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are:

Additional System Resources
System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a MAC, low voltage detection, and power on reset. The merits of each system resource are:
Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks may be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Additional Digital resources and clocks optimized for CSD. Support "RTC" block into digital peripheral logic. A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math and digital filters. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs.

Analog-to-Digital converters (Single or Dual, with 8-bit resolution) Pin-to-pin Comparator Single ended comparators with absolute (1.3V) reference or 5-bit DAC reference 1.3V reference (as a System Resource)

Analog blocks are provided in columns of four, which include CT-E (Continuous Time) and SC-E (Switched Capacitor) blocks. These devices provide limited functionality Type "E" analog blocks. Figure 2. Analog System Block Diagram
Array Input Configuration
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. The following table lists the resources available for specific PSoC device groups. Table 1. PSoC Device Characteristics PSoC Part Number Digital IO up to 64 up to 44 up to 44 up to 38 up to 28 up to 24 up to 24 up to 26 Analog Columns Analog Blocks 4 4 4 4 2 4 2 2 12 12 12 6a 4a 6a 6 4 Page 3 of 27
[+] Feedback
ACE00 ASE10
ACE01 ASE11
ACE10
ACE11
CY8C29x66 CY8C27x66 CY8C27x43 CY8C22x45 CY8C21x34 CY8C21345 CY8C24x23 CY8C24x33
4 2 2 2 1 1 1 1
16 8 8 8 4 4 4 4
12 12 12 10 28 10 12 12
Block Array
AmuxL
AmuxR P0[0:7]
ACI2[3:0]
10 bit SAR ADC
Analog Reference
Interface to Digital System Reference Generators
a. Limited analog functionality.
AGND
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-43084 Rev. *H
Analog Outputs 4 4 4 0 0 0 2 2
ACI0[1:0]
ACI1[1:0]
ACI1[1:0]
ACI1[1:0]
Analog Inputs
Digital Blocks
Digital Rows
CY8C21345, CY8C22345, CY8C22545
Getting Started
The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming details, see the PSoC Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc.
Development Tools
PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC programmable system-on-chip controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip-Level View The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools.
Application Notes
Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here: www.cypress.com/psoc. Select Application Notes under the Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736.
Document Number: 001-43084 Rev. *H
Page 4 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.
Designing with PSoC Designer
The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select components 2. Configure components 3. Organize and Connect 4. Generate, Verify, and Debug
Select Components
Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called "drivers" and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view, the components are called "user modules". User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and programmable system-on-chip varieties.
Configure Components
Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop down menus. Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in the PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.
Document Number: 001-43084 Rev. *H
Page 5 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Organize and Connect
You can build signal chains at the chip level by interconnecting user modules to each other and the IO pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer's output to a digital signal, and a PWM to control the fan. In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources.
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this data sheet. Table 2. Acronyms Acronym AC ADC API CPU CT DAC DC EEPROM FSR GPIO ICE IDE IO IPOR LSb LVD MSb PC POR PPOR PSoC(R) PWM RAM ROM SC SMP Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current electrically erasable programmable read-only memory full scale range general purpose IO in-circuit emulator integrated development environment input/output imprecise power on reset least significant bit low voltage detect most significant bit program counter power on reset precision power on reset Programmable System-on-Chip pulse width modulator random access memory read only memory switched capacitor switch mode pump
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move on to developing code for the project, perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 5 on page 9 lists all the abbreviations used to measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal.
Document Number: 001-43084 Rev. *H
Page 6 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Pinouts
This PSoC device family is available in a variety of packages that are listed in the following tables. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.
CY8C22345, CY8C21345 28-Pin SOIC
Table 3. Pin Definitions Type Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 IO IO IO IO IO IO IO IO IO IO IO IO Input MR MR MR I, MR I, MR I, MR I, MR I, MR Power IO IO IO IO Digital Analog IO IO IO IO IO IO IO IO I, MR I, ML I, ML I, ML I, ML ML ML ML Power ML ML ML ML Power MR MR MR MR Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] Vss P1[7] P1[5] P1[3] P1[1]* Vss P1[0]* P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Supply Voltage To Compare Column 1 Active High Pin Reset with Internal Pull Down Optional External Clock Input (EXT-CLK) I2C Serial Clock (SCL), ISSP-SCLK Ground Connection I2C Serial Clock (SCL), ISSP-SDATA Ground Connection I2C Serial Clock (SCL) I2C Serial Data (SDA) To Compare Column 0 Optional ADC External Vref Description Integration Capacitor for MR Integration Capacitor for ML Figure 3. Pin Diagram
AI, MR, P0[7] AI, ML, P0[5] AI, ML, P0[3] AI, ML, P0[1] AI, ML, P2[7] ADC_Ext_Vref, ML, P2[5] ML, P2[3] ML, P2[1] Vss I2C SCL, ML, P1[7] I2C SDA, ML, P1[5] ML, P1[3] I2C SCL, ML, P1[1] Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SOIC
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Vdd P0[6], MR, AI P0[4], MR, AI P0[2], MR, AI P0[0], MR, AI P2[6], MR, AI P2[4], MR P2[2], MR P2[0], MR XRES P1[6], MR P1[4], MR, EXTCLK P1[2], MR P1[0], MR, I2C SDATA
LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input, * ISSP pin which is not HiZ at POR.
Document Number: 001-43084 Rev. *H
Page 7 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
CY8C22545 44-Pin TQFP
Table 4. Pin Definitions Type Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 IO IO IO IO IO IO IO IO IO IO Power MR MR MR I, MR I, MR I, MR I, MR IO IO IO IO IO IO IO IO Input MR MR MR IO IO IO IO IO IO IO IO Power MR MR MR MR MR MR MR MR IO IO IO Power ML ML ML ML ML ML ML ML Digital IO IO IO Power ML ML ML Analog ML ML ML Pin Name P2[5] P2[3] P2[1] Vdd P4[5] P4[3] P4[1] Vss P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1]* Vss P1[0]* P1[2] P1[4] P1[6] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] Vss P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] To Compare Column 1 Ground Connection Active High Pin Reset with Internal Pull Down Optional External Clock Input (EXTCLK) Crystal (XTALin), I2C Serial Clock (SCL), TC SCLK Ground Connection Crystal (XTALout), I2C Serial Data (SDA), TC SDATA I2C Serial Clock (SCL) I2C Serial Data (SDA) Ground Connection Supply Voltage
ADC_Ext_Vref, ML, P2[5] ML, P2[3] ML, P2[1] Vdd ML, P4[5] ML, P4[3] ML, P4[1] Vss ML, P3[7] ML, P3[5] ML, P3[3] 1 2 3 4 5 6 7 8 9 10 11 12
Figure 4. Pin Diagram Description
P0[5], ML, AI P0[7], MR, AI Vdd P2[7], ML, AI P0[1], ML, AI P0[3], ML, AI P0[4], MR, AI P0[2], MR, AI P0[0], MR, AI P2[6], MR, AI 35 34 MR, P1[6] MR, P3[0] 21 22 33 32 31 30 29 28 27 26 25 24 23 P2[4], MR P2[2], MR P2[0], MR Vss P4[4], MR P4[2], MR P4[0], MR XRES P3[6], MR P3[4], MR P3[2], MR P0[6], MR, AI
Optional ADC External Vref
44
43 42
41 40
TQFP
13 14 15 16
17
ML, P1[3] I2C SCL, XTALin, ML, P1[1]
I2C SCL, ML, P1[7] I2C SDA, ML, P1[5]
ML, P3[1]
Document Number: 001-43084 Rev. *H
Vss I2C SDA, XTALout, MR, P1[0]
MR, P1[2] EXTCLK, MR, P1[4]
18 19
20
39 38 37 36
Page 8 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Table 4. Pin Definitions (continued) Type Pin No. 38 39 40 41 42 43 44 IO IO IO IO IO Digital IO Power I, MR I, ML I, ML I, ML I, ML Analog I, MR Pin Name P0[6] Vdd P0[7] P0[5] P0[3] P0[1] P2[7] To Compare Column 0 Supply Voltage Integration Capacitor for MR Integration Capacitor for ML Description
LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input, * ISSP pin which is not HiZ at POR.
Register Reference
This section lists the registers of this PSoC device family by mapping tables. For detailed register information, refer the PSoC Programmable System-on Chip Technical Reference Manual.
Register Mapping Tables
The PSoC device has a total register address space of 512 bytes. The register space is also referred to as IO space and is broken into two parts. The XOI bit in the Flag register determines which bank the user is currently in. When the XOI bit is set, the user is said to be in the "extended" address space or the "configuration" registers. Note In the following register mapping tables, blank fields are Reserved and must not be accessed.
Register Conventions
Abbreviations Used The register conventions specific to this section are listed in the following table. Table 5. Abbreviations Convention RW R W L C # Description Read and write register or bit(s) Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific
Document Number: 001-43084 Rev. *H
Page 9 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Table 6. Register Map Bank 0 Table: User Space
Access Access Access Access RW RW RW RW RW RW RW RW # # RW # RW RW RW RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RW RW RW RW W W R R RW RW RW RW # # # # # # # I RW RW RW # RW Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC Name Name Name Name
00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW CSD0_DR0_L 11 RW CSD0_DR1_L 12 RW CSD0_CNT_L 13 RW CSD0_CR0 14 RW CSD0_DR0_H 15 RW CSD0_DR1_H 16 RW CSD0_CNT_H 17 RW CSD0_CR1 18 RW CSD1_DR0_L 19 RW CSD1_DR1_L 1A RW CSD1_CNT_L 1B RW CSD1_CR0 1C RW CSD1_DR0_H 1D RW CSD1_DR1_H 1E RW CSD1_CNT_H 1F RW CSD_CR1 DBC00DR0 20 # AMX_IN DBC00DR1 21 W AMUX_CFG DBC00DR2 22 RW PWM_CR DBC00CR0 23 # ARF_CR DBC01DR0 24 # CMP_CR0 DBC01DR1 25 W ASY_CR DBC01DR2 26 RW CMP_CR1 DBC01CR0 27 # DCC02DR0 28 # ADC0_CR DCC02DR1 29 W ADC1_CR DCC02DR2 2A RW SADC_DH DCC02CR0 2B # SADC_DL DCC03DR0 2C # TMP_DR0 DCC03DR1 2D W TMP_DR1 DCC03DR2 2E RW TMP_DR2 DCC03CR0 2F # TMP_DR3 DBC10DR0 30 # DBC10DR1 31 W DBC10DR2 32 RW ACB00CR1* DBC10CR0 33 # ACB00CR2* DBC11DR0 34 # DBC11DR1 35 W DBC11DR2 36 RW ACB01CR1* DBC11CR0 37 # ACB01CR2* DCC12DR0 38 # DCC12DR1 39 W DCC12DR2 3A RW DCC12CR0 3B # DCC13DR0 3C # Shaded fields are Reserved and must not be accessed.
PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72* 73* 74 75 76* 77* 78 79 7A 7B 7C
# W RW # # W RW # # W RW # # W RW # R W R # R W R RW R W R # R W R RW RW RW RW RW # # RW RW # # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
80* RW 81 RW 82 RW 83 RW ASD11CR0* 84* RW 85 RW 86 RW 87 RW 88 RW PWMVREF0 89 RW PWMVREF1 8A RW IDAC_MODE 8B RW PWM_SRC 8C RW TS_CR0 8D RW TS_CMPH 8E RW TS_CMPL 8F RW TS_CR1 90 RW CUR PP 91 RW STK_PP 92 RW PRV PP 93 RW IDX_PP 94 RW MVR_PP 95 RW MVW_PP 96 RW I2C0_CFG 97 RW I2C0_SCR 98 RW I2C0_DR 99 RW I2C0_MSCR 9A RW INT_CLR0 9B RW INT_CLR1 9C RW INT_CLR2 9D RW INT_CLR3 9E RW INT_MSK3 9F RW INT_MSK2 A0 INT_MSK0 A1 INT_MSK1 A2 INT_VC A3 RES_WDT A4 DEC_DH A5 DEC_DL A6 DEC _CR0* A7 DEC_CR1* A8 W MUL0_X A9 W MUL0_Y AA R MUL0_DH AB R MUL0_DL AC RW ACC0_DR1 AD RW ACC0_DR0 AE RW ACC0_DR3 AF RW ACC0_DR2 RDI0RI B0 RW CPU A RDI0SYN B1 RW CPU_T1 RDI0IS B2 RW CPU_T2 RDI0LT0 B3 RW CPU_X RDI0LT1 B4 RW CPU PCL RDI0RO0 B5 RW CPU_PCH RDI0RO1 B6 RW CPU_SP RDI0DSM B7 RW CPU_F RDI1RI B8 RW CPU_TST0 RDI1SYN B9 RW CPU_TST1 RDI1IS BA RW CPU_TST2 RDI1LT0 BB RW CPU TST3 RDI1LT1 BC RW DAC1_D # Access is bit specific. * has a different meaning.
ASC10CR0*
Document Number: 001-43084 Rev. *H
Page 10 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Table 6. Register Map Bank 0 Table: User Space (continued)
Access Access Access Access RW # # RW RW RW RW RW RW RW RW # RW RW RW # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW W W RW W RW RW RW RW # # # # Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) FD FE FF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 Addr (1,Hex) Name Name Name Name Name
DCC13DR1 3D W DCC13DR2 3E RW DCC13CR0 3F # Shaded fields are Reserved and must not be accessed.
7D 7E 7F
RW RW RW
RDI1RO0 BD RW DAC0_D RDI1RO1 BE RW CPU_SCR1 RDI1DSM BF RW CPU_SCR0 # Access is bit specific. * has a different meaning.
Table 7. Register Map Bank 1 Table: Configuration Space
Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name ASC10CR0*
PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1
0 RW 1 RW 2 RW 3 RW 4 RW 5 RW 6 RW 7 RW 8 RW 9 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW CMP0CR1 11 RW CMP0CR2 12 RW 13 RW VDAC50CR0 14 RW CMP1CR1 15 RW CMP1CR2 16 RW 17 RW VDAC51CR0 18 RW CSCMPCR0 19 RW CSCMPGOEN 1A RW CSLUTCR0 1B RW CMPCOLMUX 1C RW CMPPWMCR 1D RW CMPFLTCR 1E RW CMPCLK1 1F RW CMPCLK0 DBC00FN 20 RW CLK_CR0 DBC00IN 21 RW CLK_CR1 DBC00OU 22 RW ABF_CR0 DBC00CR1 23 RW AMD_CR0 DBC01FN 24 RW CMP_GO_EN DBC01IN 25 RW CMP_GO_EN1 DBC01OU 26 RW AMD_CR1 DBC01CR1 27 RW ALT_CR0 DCC02FN 28 RW ALT_CR1 DCC02IN 29 RW CLK_CR2 DCC02OU 2A RW DBC02CR1 2B RW CLK_CR3 DCC03FN 2C RW TMP_DR0 DCC03IN 2D RW TMP_DR1 DCC03OU 2E RW TMP_DR2 DBC03CR1 2F RW TMP_DR3 DBC10FN 30 RW DBC10IN 31 RW DBC10OU 32 RW ACB00CR1* DBC10CR1 33 RW ACB00CR2* Shaded fields are Reserved and must not be accessed.
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
80* RW 81 RW 82 RW 83 RW ASD11CR0* 84* RW 85 RW 86 RW 87 RW 88 RW 89 RW 8A RW 8B RW 8C RW 8D RW 8E RW 8F RW 90 RW GDI_O_IN 91 RW GDI_E_IN 92 RW GDI_O_OU 93 RW GDI_E_OU 94 RW 95 RW 96 RW 97 RW 98 RW MUX_CR0 99 RW MUX_CR1 9A RW MUX_CR2 9B RW MUX_CR3 9C RW DAC_CR1# 9D RW OSC_GO_EN 9E RW OSC_CR4 9F RW OSC_CR3 GDI_O_IN_CR A0 RW OSC_CR0 GDI_E_IN_CR A1 RW OSC_CR1 GDI_O_OU_CR A2 RW OSC_CR2 GDI_E_OU_CR A3 RW VLT_CR RTC_H A4 RW VLT_CMP RTC_M A5 RW ADC0_TR* RTC_S A6 RW ADC1_TR* RTC_CR A7 RW V2BG_TR SADC_CR0 A8 RW IMO_TR SADC_CR1 A9 RW ILO_TR SADC_CR2 AA RW BDG_TR SADC_CR3TRIM AB RW ECO_TR SADC_CR4 AC RW MUX_CR4 I2C0_AD AD RW MUX_CR5 AE RW MUX_CR6 AF RW MUX_CR7 RDI0RI B0 RW CPU A RDI0SYN B1 RW CPU_T1 RDI0IS B2 RW CPU_T2 RDI0LT0 B3 RW CPU_X # Access is bit specific. * has a different meaning.
Document Number: 001-43084 Rev. *H
Page 11 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Table 7. Register Map Bank 1 Table: Configuration Space (continued)
Access Access Access Access # # # I RW W RW SW RW # # Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Name Name Name Name
DBC11FN 34 RW DBC11IN 35 RW DBC11OU 36 RW ACB01CR1* DBC11CR1 37 RW ACB01CR2* DCC12FN 38 RW DCC12IN 39 RW DCC12OU 3A RW DBC12CR1 3B RW DCC13FN 3C RW DCC13IN 3D RW DCC13OU 3E RW DBC13CR1 3F RW Shaded fields are Reserved and must not be accessed.
74 75 76* 77* 78 79 7A 7B 7C 7D 7E 7F
RW RW RW RW RW RW RW RW RW RW RW RW
RDI0LT1 B4 RW CPU_PCL RDI0RO0 B5 RW CPU_PCH RDI0RO1 B6 RW CPU_SP RDI0DSM B7 RW CPU_F RDI1RI B8 RW FLS_PR0 RDI1SYN B9 RW FLS TR RDI1IS BA RW FLS_PR1 RDI1LT0 BB RW RDI1LT1 BC RW FAC_CR0 RDI1RO0 BD RW DAC_CR0# RDI1RO1 BE RW CPU_SCR1 RDI1DSM BF RW CPU_SCR0 # Access is bit specific. * has a different meaning.
Document Number: 001-43084 Rev. *H
Page 12 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Electrical Specifications
This section presents the DC and AC electrical specifications of this PSoC device family. For the latest electrical specifications, check the most recent data sheet by visiting the web at http://www.cypress.com/psoc. Specifications are valid for -40C TA 85C and TJ 100C, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40C TA 70C and TJ 82C. Figure 5. Voltage versus Operating Frequency
5.25
4.75 Vdd Voltage 3.00 93 kHz
The following table lists the units of measure that are used in this section. Table 8. Units of Measure Symbol C dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm micro ampere micro farad micro henry microsecond micro volts micro volts root-mean-square Unit of Measure degree Celsius W mA ms mV nA ns nV W pA pF pp ppm ps sps s V Symbol Unit of Measure micro watts milli-ampere milli-second milli-volts nano ampere nanosecond nanovolts ohm pico ampere pico farad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts
lid n g Va rati n e io Op Reg
12 MHz CPU Frequency 24 MHz
Document Number: 001-43084 Rev. *H
Page 13 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 9. Absolute Maximum Ratings Symbol Description TSTG Storage Temperature TA Vdd VIO VIOz IMIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tristate Maximum Current into any Port Pin Electro Static Discharge Voltage Latch up Current Min -55 -40 -0.5 Vss - 0.5 Vss - 0.5 -25 2000 - Typ - - - - - - - - Max +100 +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 - 200 Units C C V V V mA V mA Human Body Model ESD Notes Higher storage temperatures reduce data retention time
Operating Temperature
Table 10. Operating Temperature Symbol Description TA Ambient Temperature TJ Junction Temperature Min -40 -40 Typ - - Max +85 +100 Units Notes C C The temperature rise from ambient to junction is package specific. See Table 31 on page 25. The user must limit the power consumption to comply with this requirement.
Document Number: 001-43084 Rev. *H
Page 14 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
DC Electrical Characteristics
DC Chip Level Specifications Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C, and are for design guidance only, unless specified otherwise. Table 11. DC Chip Level Specifications Symbol Vdd IDD Description Supply Voltage Supply Current Min 3.0 - Typ - 7 Max 5.25 12 Units Notes V See Table 18 on page 17 mA Conditions are Vdd = 5.0V, 25C, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz VC2 = 93.75 kHz VC3 = 93.75 kHz Conditions are Vdd = 3.3V TA = 25C, CPU = 3 MHz 48 MHz = Disabled VC1 = 1.5 MHz, VC2 = 93.75 kHz VC3 = 93.75 kHz Conditions are with internal slow speed oscillator, Vdd = 3.3V -40C <= TA <= 55C Conditions are with internal slow speed oscillator, Vdd = 3.3V 55C < TA <= 85C Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, -40C <= TA <= 55C Conditions are with properly loaded, 1W max, 32.768 kHz crystal. Vdd = 3.3 V, 55C < TA <= 85C Trimmed for appropriate Vdd
IDD3
Supply Current
-
4
7
mA
ISB
Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDTa Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperaturea Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal a Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature a Reference Voltage (Bandgap)
-
3
6.5
A A A A
ISBH
-
4
25
ISBXTL
-
4
7.5
ISBXTLH
-
5
26
VREF
1.275
1.3
1.325
V
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar functions enabled.
DC General Purpose IO Specifications Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only, unless otherwise specified. Table 12. DC GPIO Specifications Symbol RPU RPD VOH Description Pull up Resistor Pull down Resistor High Output Level Min 4 4 Vdd - 1.0 Typ 5.6 5.6 - Max 8 8 - Units k k V IOH = 10 mA, Vdd = 4.75 to 5.25V (80 mA maximum combined IOH budget) IOL = 25 mA, Vdd = 4.75 to 5.25V (100 mA maximum combined IOL budget) Vdd = 3.0 to 5.25 Vdd = 3.0 to 5.25 Notes
VOL
Low Output Level
-
-
0.75
V
VIL VIH
Input Low Level Input High Level
- 2.1
- -
0.8
V V
Document Number: 001-43084 Rev. *H
Page 15 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Table 12. DC GPIO Specifications (continued) Symbol VH IIL CIN COUT Description Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output Min - - - - Typ 60 1 3.5 3.5 Max - - 10 10 Units mV nA pF pF Notes Gross tested to 1 A Package and pin dependent. Temp = 25C Package and pin dependent. Temp = 25C
DC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C respectively. Typical parameters apply to 5V or 3.3V at 25C and are for design guidance only. Table 13. 5V DC Operational Amplifier Specifications Symbol VOSOA IEBOAa CINOA VCMOA Description Input Offset Voltage (absolute value) Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Min - - - - 0.0 Typ 2.5 10 200 4.5 - Max 15 - - 9.5 Vdd - 1 Units mV V/C pA pF V Gross tested to 1 A Package and pin dependent. Temp = 25C Notes
TCVOSOA Average Input Offset Voltage Drift
a. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.
Table 14. 3.3V DC Operational Amplifier Specifications Symbol VOSOA TCVOSOA IEBOAa CINOA VCMOA Description Input Offset Voltage (absolute value) Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Min - - - - 0 Typ 2.5 10 200 4.5 - Max 15 - - 9.5 Vdd - 1 Units mV V/C pA pF V Gross tested to 1 A Package and pin dependent. Temp = 25C Notes
a.Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.
DC Low Power Comparator Specifications Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 15. DC Low Power Comparator Specifications Symbol VREFLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC voltage offset Min 0.2 - Typ - 2.5 Max Vdd - 1 30 Units V mV
Document Number: 001-43084 Rev. *H
Page 16 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
SAR10 ADC DC Specifications
Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C and are for design guidance only. Table 16. SAR10 ADC DC Specifications Symbol Vadcvref Description Reference voltage at pin P2[5] when configured as ADC reference voltage Min 3.0 Typ - Max 5.25 Units V Notes When VREF is buffered inside ADC, the voltage level at P2[5] (when configured as ADC reference voltage) must be always maintained to be at least 300 mV less than the chip supply voltage level on Vdd pin. (Vadcvref < Vdd) Disables the internal voltage reference buffer For VDD 3.0V and Vref 3.0V For VDD < 3.0V or Vref < 3.0V For VDD 3.0V and Vref 3.0V For VDD < 3.0V or Vref < 3.0V
Iadcvref INL at 10 bits
Current when P2[5] is configured as ADC VREF Integral Nonlinearity
-2.5 -5.0 -1.5 -4.0 -
- - - - - -
0.5 2.5 5.0 1.5 4.0 150
mA LSB LSB LSB LSB
DNL at 10 bits Differential Nonlinearity SPS Sample per second
ksps Resolution 10 bits
DC Analog Mux Bus Specifications Table 17 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C and are for design guidance only. Table 17. DC Analog Mux Bus Specifications Symbol RSW Rgnd Description Switch Resistance to Common Analog Bus Resistance of Initialization Switch to gnd Min - - Typ - - Max 400 800 Units Vdd 3.00 Notes
DC POR and LVD Specifications Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C and are for design guidance only. Table 18. DC POR and LVD Specifications Symbol VPPOR1 VPPOR2 Description Vdd Value for PPOR Trip PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min - Typ 2.82 4.55 Max 2.95 4.70 Units V V Notes Vdd must be greater than or equal to 3.0V during startup, reset from the XRES pin, or reset from Watchdog.
VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7
2.95 3.06 4.37 4.50 4.62 4.71
3.02 3.13 4.48 4.64 4.73 4.81
3.09 3.20 4.55 4.75 4.83 4.95
V V V V V V
Document Number: 001-43084 Rev. *H
Page 17 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
DC Programming Specifications Table 19 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C and are for design guidance only. Table 19. DC Programming Specifications Symbol Description VddIWRITE Supply Voltage for Flash Write Operations IDDP VILP Supply Current during Programming or Verify Input Low Voltage during Programming or Verify VIHP Input High Voltage during Programming or Verify IILP Input Current when Applying Vilp to P1[0] or P1[1] during Programming or Verify IIHP Input Current when Applying Vihp to P1[0] or P1[1] during Programming or Verify VOLV Output Low Voltage during Programming or Verify VOHV Output High Voltage during Programming or Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)a FlashDR Flash Data Retention Min 2.70 - - 2.2 - - - Vdd - 1.0 50,000 1,800,000 10 Typ - 5 - - - - - - - - - Max - 25 0.8 - 0.2 1.5 Vss + 0.75 Vdd - - - Units V mA V V mA mA V V - - Years Erase/write cycles per block Erase/write cycles Driving internal pull down resistor Driving internal pull down resistor Notes
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). b For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-43084 Rev. *H
Page 18 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
AC Electrical Characteristics
AC Chip Level Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C and are for design guidance only. Table 20. 5V and 3.3V AC Chip-Level Specifications
Symbol FIMO24 Description Internal Main Oscillator Frequency for 24 MHz Min 22.8 Min(%) Typ 24 Max 25.2a,b,c Max(%) Units Notes MHz Trimmed for 5V or 3.3V operation using factory trim values. See Figure 5 on page 13. SLIMO mode = 0 < 85 8 MHz Trimmed for 5V or 3.3V operation using factory trim values. See Figure 5 on page 13. SLIMO mode = 0 < 85 MHz 24 MHz only for SLIMO mode = 0 MHz MHz Refer to Table 25 on page 21. MHz kHz kHz The ILO is not adjusted with the factory trim values until after the CPU starts running. See the "System Resets" section in the Technical Reference Manual. ns s % ps MHz s
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
8
6
6.35a,b,c
FCPU1 FCPU2 FBLK5 FBLK33 F32K1 F32KU
CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency (5V Nominal) Digital PSoC Block Frequency (3.3V Nominal) Internal Low Speed Oscillator Frequency Untrimmed Internal Low Speed Oscillator Frequency
0
0.93 0.93 0 0 15 5
24 12 48 24 32 -
24.6a,b 12.3b,c 49.2a,b,d 24.6
b,d
75 -
Jitter32k TXRST DC24M FMAX TRAMP
32 kHz RMS Period Jitter External Reset Pulse Width 24 MHz Duty Cycle Maximum frequency of signal on row input or row output Supply Ramp Time
- 10 40 - - 25
100 - 50 300 - -
-- 60 600 12.3 -
Jitter24M1 24 MHz Period Jitter (IMO)
a. Valid only for 4.75V < Vdd < 5.25V. b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. d. Refer to the individual user module data sheets for information on maximum frequencies for user modules.
Figure 6. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F 24M
Figure 7. 32 kHz Period Jitter (ILO) Timing Diagram
Jitter32k
F 32K1
Document Number: 001-43084 Rev. *H
Page 19 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
AC General Purpose IO Specifications Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C and are for design guidance only. Table 21. 5V and 3.3V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 3 2 7 7 Typ - - - 27 22 Max 12 18 18 - - Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90%
Figure 8. GPIO Timing Diagram
90% GPIO Pin Output Voltage 10%
TRiseF TRiseS
TFallF TFallS
AC Operational Amplifier Specifications Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C and are for design guidance only. Table 22. AC Operational Amplifier Specifications Symbol TCOMP Description Comparator Mode Response Time, 50 mV Min Typ Max 100 Units ns Vdd 3.0V Notes
AC Low Power Comparator Specifications Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 23. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Min - Typ - Max 50 Units Notes s 50 mV overdrive comparator reference set within VREFLPC
AC Analog Mux Bus Specifications Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C and are for design guidance only. Table 24. AC Analog Mux Bus Specifications Symbol FSW Switch Rate Description Min - Typ - Max 3.17 Units MHz Notes
Document Number: 001-43084 Rev. *H
Page 20 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
AC Digital Block Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V, at 25C and are for design guidance only. Table 25. 5V and 3.3V AC Digital Block Specifications Function All Functions Timer Description Maximum Block Clocking Frequency (> 4.75V) Maximum Block Clocking Frequency (< 4.75V) Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With or Without Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) Maximum Input Clock Frequency 20 50 50 - - - - - 50 - - - - - - - - - - - - - - - - - - - - 49.2 49.2 24.6 8.2 4.1 - 24.6 49.2 24.6 49.2 ns ns ns MHz 4.75V < Vdd < 5.25V MHz 4.75V < Vdd < 5.25V MHz MHz Maximum data rate at 4.1 MHz due to 2 x over clocking MHz ns MHz Maximum data rate at 3.08 MHz due to 8 x over clocking MHz Maximum data rate at 6.15 MHz due to 8 x over clocking MHz Maximum data rate at 3.08 MHz due to 8 x over clocking MHz Maximum data rate at 6.15 MHz due to 8 x over clocking 50 - - 50 - -
a
Min
Typ
Max 49.2 24.6
Units
Notes
MHz 4.75V < Vdd < 5.25V MHz 3.0V < Vdd < 4.75V ns MHz 4.75V < Vdd < 5.25V MHz ns MHz 4.75V < Vdd < 5.25V MHz
- - - - - -
- 49.2 24.6 - 49.2 24.6
CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Transmitter Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Maximum Input Clock Frequency Maximum Input Clock Frequency with Vdd 4.75V, 2 Stop Bits Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency with Vdd 4.75V, 2 Stop Bits
a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
AC External Clock Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C and are for design guidance only. Table 26. 5V AC External Clock Specifications Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description Min 0.093 20.6 20.6 150 Typ - - - - Max 24.6 5300 - - Units MHz ns ns s
Document Number: 001-43084 Rev. *H
Page 21 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Table 27. 3.3V AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU Clock divide by 1 Min 0.093 Typ - Max 12.3 Units Notes MHz Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. MHz If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. ns ns s
FOSCEXT
Frequency with CPU Clock divide by 2 or greater
0.186
-
24.6
- - -
High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch
41.7 41.7 150
- - -
5300 - -
SAR10 ADC AC Specifications
Table 28 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 28. SAR10 ADC AC Specifications Symbol Freq3 Freq5 Description Input clock frequency 3V Input clock frequency 5V Min - - Typ - - Max 2.7 2.7 Units MHz MHz
AC Programming Specifications Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V, or 3.3V at 25C and are for design guidance only. Table 29. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK FSCLK3 TERASEB TWRITE TDSCLK TDSCLK3 Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Frequency of SCLK3 Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Min 1 1 40 40 0 0 - - - - Typ - - - - - - 15 30 - - Max 20 20 - - 8 6 - - 55 65 Units ns ns ns ns MHz MHz VDD < 3.6V ms ms ns ns 3.6 < Vdd; at 30 pF Load 3.0 Vdd 3.6; at 30 pF Load Notes
Document Number: 001-43084 Rev. *H
Page 22 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
AC I2C Specifications Table 30 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, and 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 30. AC Characteristics of the I2C SDA and SCL Pins for Vdd 3.0V Symbol FSCLI2C THDSTAI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the Input Filter Standard Mode Min Max 0 100 4.0 - Fast Mode Min Max 0 400 0.6 - Units kHz s s s s s ns s s ns
TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C
a.
4.7 4.0 4.7 0 250 4.0 4.7 -
- - - - - - - -
1.3 0.6 0.6 0 100a 0.6 1.3 0
- - - - - - - 50
A Fast-Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Figure 9. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Sr
P
S
Document Number: 001-43084 Rev. *H
Page 23 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Packaging Information
This section provides the packaging specifications for this PSoC device with the thermal impedances for each package, and the typical package capacitance on crystal pins.
Packaging Dimensions
Figure 10. 28-Pin SOIC
NOTE :
PIN 1 ID
1. JEDEC STD REF MO-119 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX.
14
1
0.291[7.39] 0.300[7.62]
4. PACKAGE WEIGHT 0.85gms
*
0.394[10.01] 0.419[10.64] 15 28
0.026[0.66] 0.032[0.81]
PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG.
0.697[17.70] 0.713[18.11] 0.092[2.33] 0.105[2.67]
SEATING PLANE
0.004[0.10] 0.013[0.33] 0.050[1.27] TYP. 0.019[0.48] 0.004[0.10] * 0.0118[0.30] 0.015[0.38] 0.050[1.27]
0.0091[0.23] 0.0125[3.17]
51-85026 *D
Figure 11. 44-Pin TQFP
12.000.25 SQ 10.000.10 SQ 44 34 0 MIN. 1 33 0.370.05 STAND-OFF 0.05 MIN. 0.15 MAX. R. 0.08 MIN. 0.20 MAX. 0.25 GAUGE PLANE
R. 0.08 MIN. 0.20 MIN. 0.20 MIN. 0.80 B.S.C. 1.00 REF.
0-7 0.600.15
11
23
DETAIL 12 22
A
NOTE: 1. JEDEC STD REF MS-026
SEATING PLANE 1.60 MAX. 121 (8X)
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
1.400.05 0.10 0.20 MAX. SEE DETAIL
A
51-85064 *C
Document Number: 001-43084 Rev. *H
Page 24 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Thermal Impedances
Table 31. Thermal Impedances per Package Package 28 SOIC 44 TQFP * TJ = TA + POWER x JA Typical JA * 68C/W 61C/W
Capacitance on Crystal Pins
Table 32. Typical Package Capacitance on Crystal Pins Package 28 SOIC 44 TQFP Package Capacitance 2.7 pF 2.6 pF
Ordering Information
The following table lists the key package features and ordering codes of this PSoC device family. Table 33. PSoC Device Family Key Features and Ordering Information Analog Outputs 0 0 0 Analog Blocks (Columns of 3) Flash (Kbytes) Digital IO Pins Analog Inputs Digital Blocks (Rows of 4) Temperature Range RAM (Bytes)
Package
Ordering Code
28 SOIC 28 SOIC 44 TQFP
CY8C21345-24SXI CY8C22345-24SXI CY8C22545-24AXI
8 16 16
512B 1K 1K
-40C to +85C -40C to +85C -40C to +85C
4 8 8
6 6 6
24 24 38
10 10 10
Ordering Code Definitions
CY 8 C 2x xxx-SPxx
Package Type: P = PDIP S = SOIC PV = SSOP LF = MLF A = TQFP Speed: 24 MHz Part Number Family Code (21, 22) Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Semiconductor Thermal Rating: C = Commercial I = Industrial E = Extended
Document Number: 001-43084 Rev. *H
Page 25 of 27
XRES Pin Y Y Y
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Document History Page
Document Title: CY8C21345, CY8C22345, CY8C22545 PSoC(R) Programmable System-on-ChipTM Document Number: 001-43084 Revision ** *A ECN 2251907 2506377 Orig. of Change PMP/AESA EIJ/AESA Submission Date See ECN See ECN New Data sheet Changed data sheet status to "Preliminary". Changed part numbers to CY8C22x45. Updated data sheet template. Added 56-Pin OCD information. Added: "You must put filters on intended ADC input channels for anti-aliasing. This ensures that any out-of-band content is not folded into the Input Signal Band." To Section Analog System on page 3. Corrected Minimum Electro Static Discharge Voltage in Table 9 on page 14. Updated Features on page 1, PSoC Core on page 2, Analog System on page 3. Changed DBB to DBC, and DCB to DCC in Register Tables Table 6 on page 10 and Table 7 on page 11. Removed INL at 8 bit reference in Table 16 on page 17. Changed IDD3 value Table 18 on page 17 Typ:3.3 mA, Max 6 mA Added "3.0V < Vdd < 3.6V and -40C < TA < 85C, IMO can guarantee 5% accuracy only" to Table 20 on page 19. Updated data sheet template. Updated data sheet status to "Final". Updated block diagram on page 1. Removed CY8C22045 56-Pin OCD information. Added part numbers CY8C21345, CY8C22345, and CY8C22545. For more details, see CDT 31271. Confirmed CY8C22345 and CY8C21345 have same pinout on page 8. Confirmed that IMO has 5% accuracy in Table 20 on page 19. Updated Table 16. SAR10 ADC DC Specifications and Table 29 AC Programming Specifications. Title changed to "CY8C21345, CY8C22345, CY8C22545 PSoC(R) Programmable System-on-ChipTM" Updated INL, DNL information in Table 16 on page 17, Development Tools on page 4, and TDSCLK parameter in Table 29 on page 22. Updated section Features on page 1. Added parameter "F32KU" and added Min% and Max % to parameter "FIMO6" in Table 20 on page 19, according to updated SLIMO spec. Description of Change
*B
2558750
PMP/AESA
08/28/2008
*C
2606793
NUQ/AESA
11/19/2008
*D *E
2615697 2631733
PMP/AESA PMP/PYRS
12/03/2008 01/07/2009
*F *G *H
2648800 2658078 2667311
JHU/AESA HMI/AESA JHU/AESA
01/28/2009 02/11/2009 03/16/2009
Document Number: 001-43084 Rev. *H
Page 26 of 27
[+] Feedback
CY8C21345, CY8C22345, CY8C22545
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
Products
PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com
PSoC Solutions
General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb
(c) Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-43084 Rev. *H
Revised March 16, 2009
Page 27 of 27
PSoC DesignerTM and Programmable System-on-ChipTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

▲Up To Search▲

Price & Availability of CY8C22345-24SXI

	To Download CY8C22345-24SXI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .